#ifndef _PORT_CI_PORT_IP_CFG_H_
#define _PORT_CI_PORT_IP_CFG_H_

#include "S32K144_PORT.h"
#include "S32K144_GPIO.h"
#include "Port_Ci_Port_Ip_Types.h"

/***********************************************************************************************************************
 * Definitions
 **********************************************************************************************************************/

/*==================================================================================================
*                              SOURCE FILE VERSION INFORMATION
==================================================================================================*/
#define PORT_CI_PORT_IP_VENDOR_ID_CFG_H                       43
#define PORT_CI_PORT_IP_AR_RELEASE_MAJOR_VERSION_CFG_H        4
#define PORT_CI_PORT_IP_AR_RELEASE_MINOR_VERSION_CFG_H        4
#define PORT_CI_PORT_IP_AR_RELEASE_REVISION_VERSION_CFG_H     0
#define PORT_CI_PORT_IP_SW_MAJOR_VERSION_CFG_H                1
#define PORT_CI_PORT_IP_SW_MINOR_VERSION_CFG_H                0
#define PORT_CI_PORT_IP_SW_PATCH_VERSION_CFG_H                1

/*!
 * @addtogroup Port_Ci_Port_Ip_Cfg
 * @{
 */

/***********************************************************************************************************************
 * API
 **********************************************************************************************************************/

#if defined(__cplusplus)
extern "C" {
#endif


/*! @brief Definitions/Declarations for BOARD_InitPins Functional Group */
/*! @brief User definition pins */
#define XWSSC_RXD_PORT    IP_PTC
#define XWSSC_RXD_PIN     2U
#define XWSSC_TXD_PORT    IP_PTC
#define XWSSC_TXD_PIN     3U
#define CONSOLE_RXD_PORT    IP_PTA
#define CONSOLE_RXD_PIN     8U
#define CONSOLE_TXD_PORT    IP_PTA
#define CONSOLE_TXD_PIN     9U
#define SPI0_SCK_PORT    IP_PTB
#define SPI0_SCK_PIN     2U
#define SPI0_SIN_PORT    IP_PTB
#define SPI0_SIN_PIN     3U
#define SPI0_SOUT_PORT    IP_PTB
#define SPI0_SOUT_PIN     1U
#define SPI0_CS0_PORT    IP_PTB
#define SPI0_CS0_PIN     0U
#define GPO_LED_BLUE_PORT    IP_PTD
#define GPO_LED_BLUE_PIN     13U
#define GPO_LED_GREEN_PORT    IP_PTB
#define GPO_LED_GREEN_PIN     5U
#define GPO_LED_RED_PORT    IP_PTB
#define GPO_LED_RED_PIN     4U
#define GPI_BUTTON_PORT    IP_PTD
#define GPI_BUTTON_PIN     15U
#define LPI2C_SCL_PORT    IP_PTA
#define LPI2C_SCL_PIN     3U
#define LPI2C_SDA_PORT    IP_PTA
#define LPI2C_SDA_PIN     2U
#define FLEXIOI2C_SCL_PORT    IP_PTA
#define FLEXIOI2C_SCL_PIN     0U
#define FLEXIOI2C_SDA_PORT    IP_PTA
#define FLEXIOI2C_SDA_PIN     1U
#define CAN0_RXD_PORT    IP_PTE
#define CAN0_RXD_PIN     4U
#define CAN0_TXD_PORT    IP_PTE
#define CAN0_TXD_PIN     5U
#define CAN0_ERR_PORT    IP_PTE
#define CAN0_ERR_PIN     8U
#define CAN0_IRQ_PORT    IP_PTE
#define CAN0_IRQ_PIN     7U
#define CAN0_WAKE_PORT    IP_PTE
#define CAN0_WAKE_PIN     2U
#define CAN0_EN_PORT    IP_PTE
#define CAN0_EN_PIN     1U
#define CAN0_STB_PORT    IP_PTE
#define CAN0_STB_PIN     0U
/*! @brief User number of configured pins */
#define NUM_OF_CONFIGURED_PINS0 23
/*! @brief User configuration structure */
extern Port_Ci_Port_Ip_PinSettingsConfig g_pin_mux_InitConfigArr0[NUM_OF_CONFIGURED_PINS0];


#if defined(__cplusplus)
}
#endif

/*!
 * @}
 */
#endif /* _PORT_CI_PORT_IP_CFG_H_ */

/***********************************************************************************************************************
 * EOF
 **********************************************************************************************************************/

